1. Field of Invention
The present invention relates to a memory device. More particularly, the present invention relates to a memory device for a burn-in test and a method for screening out defective dynamic random access memory (DRAM) cells in the wafer state.
2. Description of Related Art
In general, a burn-in test is performed on a semiconductor memory device to prevent reliability problems, and more specifically, after the device has been assembled or packaged. The screened devices, if defective, cannot be repaired with a laser and re-assembled. Volume production is therefore more expensive. The burn-in test is usually performed at a high voltage and high temperature; the semiconductor memory device is operated in read or write mode to screen out possible existent defects in, for example, the gate oxide film of the cell transistor, the storage node and the p/n junctions, the cell capacitor insulator film, the adjacent word lines, the adjacent bit lines, the word lines and the bit lines. But the word line to be active is responsive to the row address in sequence, especially for a DRAM device, and is dependent on the number of refresh cycles. For example, one particular word line can be selected once every 1024 cycles for 4M DRAM, 2048 or 4096 for 16M DRAM, and 4096 or 8192 for 64M DRAM. Besides, the duty cycle of work line and the complement burn-in data “1” and “0” are considerable when evaluating the efficiency of a stressed memory cell. The stress efficiency is low if the burn-in test time cannot be increased, especially for the high-density new generation memory device. Similar problems arise for a column address to access stored data or to write in new data. If all of the word lines are active at the same time and all of the cells are refreshed simultaneously, the burn-in test time and cost is dramatically reduced, especially in the wafer stage.
In consideration of the above, some conventional art exists that includes circuits or methods to increase the burn-in efficiency of a wafer or the package stage. They are briefly described as follows:
In U.S. Pat. No. 5,265,057, all of the word lines can be selected simultaneously or in groups to stress the adjacent word line. The operation power is not applied to the device so that the stress voltage can be input, or a pass gate that connects the boost circuit to the word line driver is turned off, after which the stress voltage can come from an external test pad. The burn-in data is input through the bit line precharge device and is applied to the bit line pair. Then, the burn-in data are written into the cell.
In U.S. Pat. No. 5,293,340, the stress voltage is applied to a predetermined external test pad. Two additional NMOS are then coupled to the bit line pair, respectively, through a PMOS to drive all of the word lines simultaneously, in order to input the burn-in data.
In U.S. Pat. No. 5,381,373, as device operates in a burn-in process, the boost circuit is inactive and shorts the word line power supply to the device operation power supply. The burn-in data also come from the bit line precharge device, besides separating the bit line precharge generator and cell plate voltage generator.
In U.S. Pat. Nos. 5,590,079 and 5,790,465, two NMOS devices connect to pull the NMOS of a word line driver low and only one of the two NMOS can be turned on in normal mode or burn-in mode. In normal operation, one grounded NMOS is turned on for word line noise immunity while the other NMOS is turned on in burn-in test mode for applying the word line stress voltage.
In U.S. Pat. No. 5,638,331, a test circuit is provided to place the NMOS-type word line driver in a high-impedance state. The burn-in background data is written into the memory cell before the burn-in test mode is set, and then the operation voltage is applied to the word lien through a PMOS to stress the gate oxide film.
In U.S. Pat. No. 5,926,423, the cell plate voltage is separated from bit line precharge voltage by a CMOS pass gate at the output of voltage generator. The bit line stress voltage is transferred from the external voltage or the complementary internal input through stress transferring PMOS, then via the bit line precharge NMOS to the bit line.
In U.S. Pat. No. 6,055,199, a bit line precharge circuit is connected to an external test pad for supplying a bit line stress voltage and bit line precharge device and memory cells. Word lines are partitioned into odd and even addresses, and the bit line stress voltage is supplied via the bit line precharge device to memory cells. Then, a cell checker pattern is realized.
In U.S. Pat. No. 6,169,694, a fully on-chip wafer level burn-in test circuit is described. It includes three main circuits. A high voltage generating unit generates the word line stress voltage for screening out gate oxide defects. The bit line precharge voltage and the cell plate voltage are supplied by the bit line precharge voltage generating unit and the cell plate voltage generating unit, respectively. The burn-in data is entered through bit line precharge device and the cell plate voltage is used to stress a memory cell.
In the prior art described above, the gate oxide stress voltage can be supplied by an external power supply via a predetermined external test pad or an internal high voltage generator. No matter what kind of voltage source the chip designer selects, a maximum current that voltage source can supply always exists. For example, a word line defect is burned out successfully during the burn-in test, or there are inherent word line related defects. Both result in a leakage path on the word line. In an extreme case, this defect causes the word line to short directly to the ground, so the leakage current is too large to be supplied by the voltage source. The word line stress voltage then largely decreases because the voltage source cannot support the leakage current. When the stress voltage is reduced, the electric field across gate oxide film becomes insufficient. Therefore, no more gate oxide related defects are screened.
Further, in the conventional wafer level burn-in test method, the burn-in background data is written either through a bit line precharge device or via additional device coupled to the bit line. In such a method, the cell plate voltage needs to be separated from the bit line precharge voltage. The former is used to stress the cell capacitor insulator film and the later is used to write in burn-in data. The bit line and bit line bar usually have the same voltage level and no electric field exists between them. This method cannot screen out the defects relative to an adjacent bit line. Another disadvantage is that the separate voltage levels have different responses to ground noise, which is always something against bit line signal sensing in normal operation.